Data storage system having multi-level memory device and operating method thereof

ABSTRACT

A method for a data storage system is disclosed. The method includes providing a memory cell array, and providing N blocks in a first region of the memory cell array, N being an integer greater than 1. Each cell of each block of the N blocks is configured to store no more than N−1 bits of data. The method further includes providing a block in the second region of the memory cell array. Each cell of the block in the second region is configured to store N bits of data. The method additionally includes configuring the data storage system so that when data is programmed to the memory cell array, N pages of the data are initially stored in N respective blocks of the first region of the memory cell array, and then the N pages of the data are stored in the block of the second region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefits of priority, under 35 U.S.C §119,to Korean Patent Application No. 10-2011-0058312 filed Jun. 16, 2011,the entirety of which is incorporated by reference herein.

BACKGROUND

Exemplary embodiments relate to a memory device, and more particularly,relate to a data storage system including a multi-level memory device.

Semiconductor memory devices may be generally classified into volatilememory devices and non-volatile memory devices. Volatile memory devicesmay lose stored contents at power-off, while non-volatile memory devicesmay retain stored contents even at power-off. Nonvolatile memory devicesmay be formed of various types of memory cell transistors. Nonvolatilememory devices may include a flash memory device, a Ferroelectric RandomAccess Memory (FRAM) device, a Magnetic RAM (MRAM), a Phase change RAM(PRAM), or the like.

As a nonvolatile memory device, the flash memory device may be dividedinto NOR type flash memory devices and NAND flash memory devicesaccording to connection relationships of memory cells and bit lines. TheNOR flash memory device may have a structure in which two or more memorycell transistors are connected to one bit line in parallel. Accordingly,the NOR flash memory device may have excellent characteristics relatingto random access time. On the other hand, the NAND flash memory devicemay have a structure in which two or more memory cells are connected toone bit line in series. This structure is called the cell stringstructure. One cell string may necessitate one bit line contact.Accordingly, the NAND flash memory devices may have excellentcharacteristics relating to integration.

Memory cells of flash memory device may be determined as ON cells or OFFcells according to a threshold voltage distribution. ON cells mayrepresent erased cells, and OFF cells may represent programmed cells. Aprogrammed memory cell may have one threshold voltage belonging to oneof threshold voltage distributions each corresponding to N programstates (or, programmed data values) (N being an integer of 1 or more).

At programming, the coupling effect may be caused between selectedmemory cells and adjacent memory cells. The coupling effect may make athreshold voltage distribution corresponding to the selected memorycells become wide and a margin between adjacent threshold voltagedistributions become narrow. Such a coupling effect may be called the“electric field coupling” or “F-poly coupling”. If variation of athreshold voltage distribution corresponding to the selected memorycells and reduction of a margin between adjacent threshold voltagedistributions are caused due to the coupling effect, it may be difficultor impossible to reliably read data from memory cells. This problem mayincrease in proportion to an increase in the number of data bits beingstored per cell.

SUMMARY

In one embodiment, a data storage system is disclosed. The data storagesystem includes a nonvolatile memory device including a memory cellarray, and a memory controller configured to control the nonvolatilememory device. The memory cell array includes a first region configuredfor storing up to N−1-bit data (N being an integer greater than 1) permemory cell and a second region configured for storing N-bit data permemory cell, the first region including N memory blocks. The memorycontroller is configured to control the nonvolatile memory device toperform a buffer program operation in which N-bit data to be stored inthe second region is divisionally stored in the N memory blocks of thefirst region, and a main program operation in which the N-bit datastored in the first region is stored in the second region. The memorycontroller is configured to control the nonvolatile memory device todivisionally store, during the buffer program operation, the N-bit dataat a word line of each of the N memory blocks of the first regiondisposed at the same relative location, with respect to each block, as aword line of the second region in which the N-bit data is to be stored.

In another embodiment, an operating method of a data storage system isdisclosed. The data storage system includes a nonvolatile memory devicehaving a memory cell array divided into a first region and a secondregion, and a memory controller configured to control the nonvolatilememory device. The operating method includes performing a first programoperation in which N-bit data (N being a positive integer greaterthan 1) to be stored in the second region is divisionally stored in eachof at least N memory blocks included in the first region, and performinga second program operation in which the N-bit data stored in the firstregion is stored in the second region. Performing the first programoperation includes divisionally storing the N-bit data at a word line ofeach of the N memory blocks of the first region disposed at the samelocation relative to the memory block in which it is included as a wordline of the second region in which the N-bit data is to be stored.

In a further embodiment, a method for a data storage system isdisclosed. The method includes providing a memory cell array, andproviding N blocks in a first region of the memory cell array, N beingan integer greater than 1. Each cell of each block of the N blocks isconfigured to store no more than N−1 bits of data. The method furtherincludes providing a block in the second region of the memory cellarray. Each cell of the block in the second region is configured tostore N bits of data. The method additionally includes configuring thedata storage system so that when data is programmed to the memory cellarray, N pages of the data are initially stored in N respective blocksof the first region of the memory cell array, and then the N pages ofthe data are stored in the block of the second region.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features will become apparent from thefollowing description with reference to the following figures, whereinlike reference numerals refer to like parts throughout the variousfigures unless otherwise specified, and wherein:

FIG. 1 is a diagram illustrating an address scramble manner applied to amulti-level memory device.

FIG. 2 is a diagram showing threshold voltage distributions varied whena program operation is carried out according to 3-step programming tostore 3-bit data in each memory cell.

FIG. 3 is a diagram showing threshold voltage distributions varied whena program operation is carried out according to 3-step programming tostore 4-bit data in each memory cell.

FIG. 4 is a block diagram showing a data storage system according to anexemplary embodiment.

FIG. 5 is a diagram showing an exemplary address scramble manner of amulti-bit memory device which stores 3-bit data per cell and to which a3-step reprogram method is applied, according to certain embodiments.

FIG. 6 is a diagram showing data flow during a program operation of adata storage system where an address scramble manner illustrated in FIG.4 is applied, according to certain exemplary embodiments.

FIG. 7 is a flow chart for describing a read operation of a memorysystem illustrated in FIG. 4, according to certain exemplaryembodiments.

FIGS. 8 and 9 are diagrams illustrating data flow according to a set ofa parallel buffer program operation and a main program operationdescribed in FIG. 6, according to certain exemplary embodiments.

FIGS. 10 and 11 are diagrams illustrating a bias condition at a parallelbuffer program operation according to an exemplary embodiment.

FIG. 12 is a diagram for describing a command provided to a multi-levelmemory device to perform a program operation that includes a parallelbuffer program/read operation according to an exemplary embodiment.

FIG. 13 is a diagram for describing another command provided to amulti-level memory device to perform a program operation that includes aparallel buffer program/read operation according to an exemplaryembodiment.

FIGS. 14 to 17 are diagrams for describing various combinations on firstand second regions of a multi-bit memory device according to anexemplary embodiment.

FIG. 18 is a diagram illustrating a memory cell array having the all bitline memory architecture or the odd-even memory architecture accordingto certain exemplary embodiments.

FIG. 19 is a block diagram showing a computing system according to anexemplary embodiment.

FIG. 20 is a block diagram showing a memory controller according to anexemplary embodiment.

FIG. 21 is a block diagram showing a solid state drive according toexemplary embodiments.

FIG. 22 is a block diagram showing a storage using a solid state drivein FIG. 21 according to certain exemplary embodiments.

FIG. 23 is a block diagram showing a storage server using a solid statedrive in FIG. 21 according to certain exemplary embodiments.

FIGS. 24 to 26 are diagrams showing systems to which a data storagedevice according to exemplary embodiments.

FIG. 27 is a block diagram illustrating a memory card according toexemplary embodiments.

FIG. 28 is a block diagram illustrating a digital still camera accordingto exemplary embodiments.

FIG. 29 is a diagram illustrating various systems to which a memory cardin FIG. 28 is applied according to certain exemplary embodiments.

DETAILED DESCRIPTION

The present disclosure is described more fully hereinafter withreference to the accompanying drawings, in which various embodiments areshown. This inventive concept may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. In the drawings, the size and relativesizes of layers and regions may be exaggerated for clarity. Like numbersrefer to like elements throughout. The terminology used herein is forthe purpose of describing particular embodiments only and is notintended to be limiting of the inventive concept.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. Unless indicatedotherwise, these terms are only used to distinguish one element,component, region, layer or section from another element, component,region, layer or section. Thus, a first element, component, region,layer or section discussed below could be termed a second element,component, region, layer or section without departing from the teachingsdisclosed herein.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”,“above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”or “under” other elements or features would then be oriented “above” theother elements or features. Thus, the exemplary terms “below” and“under” can encompass both an orientation of above and below. The devicemay be otherwise oriented (rotated 90 degrees or at other orientations)and the spatially relative descriptors used herein interpretedaccordingly. In addition, it will also be understood that when a layeris referred to as being “between” two layers, it can be the only layerbetween the two layers, or one or more intervening layers may also bepresent.

As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “includes,”“including,” “comprises,” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof. As used herein,the term “and/or” includes any and all combinations of one or more ofthe associated listed items.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it can be directly on, connected, coupled, or adjacentto the other element or layer, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to”, “directly coupled to”, or “immediatelyadjacent to” another element or layer, there are no intervening elementsor layers present.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art. It will be further understood that terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe context of the relevant art and/or the present specification andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a diagram illustrating an address scramble manner applied to amulti-level memory device.

With an increase in the number of data bits stored in each memory cell,it is increasingly difficult to secure the reliability of a memorydevice storing multi-bit (or, multi-level) data, which is called amulti-level memory device, hereinafter. A representative one of factorscausing degradation of the reliability may be a variation of thresholdvoltages due to the coupling between adjacent memory cells. For example,a threshold voltage of a previously programmed memory cell may be varieddue to the coupling caused when a memory cell adjacent to a programmedmemory cell is programmed. An example of an address scramble manner maybe applied to a multi-level memory device to manage the couplingeffectively.

An address scramble manner will be described under the assumption that3-bit data is stored in one memory cell. For ease of illustration, inFIG. 1, there are illustrated only four word lines WL0 to WL3 of amemory device. A plurality of memory cells MC may be connected with eachword line.

For the memory device, there may be performed a 1-step program operation(i.e., a first program operation step) in which an initial number ofbits of data, such as two bits of data (e.g., lower 2-bit data) arestored to each memory cell in the first word line WL0. For example,during the 1-step program operation, 2-page data may be stored in thememory cells connected with the first word line WL0. This is marked{circle around (by 1)} in FIG. 1. Then, a 1-step program operation maybe made with respect to memory cells connected with the second word lineWL1. This is marked by {circle around (2)} in FIG. 1.

After the 1-step program operation is performed with respect to memorycells connected with the second word line WL1, a coarse programoperation (also called a second program operation, or 2-step programoperation) may be made with respect to the first word line WL0 which isplaced below the second word line WL1 and in which lower 2-bit data isprogrammed. This is marked by {circle around (3)} in FIG. 1. During thecoarse program operation, a third bit of data (e.g., an upper 1-bitdata) may be stored in memory cells connected with the first word lineWL0. Following the 2-step program operation of memory cells connectedwith the first word line WL0, the 1-step program operation may be madewith respect to the third word line WL2. This is marked by {circlearound (4)} in FIG. 1.

After the 1-step program operation for memory cells connected with thethird word line WL2, there may be made the 2-step program operationduring which lower 2-bit data and upper 1-bit data are stored in memorycells connected with the second word line WL1 where the lower 2-bit datais programmed. This is marked by {circle around (5)} in FIG. 1.

Following the 2-step program operation for memory cells connected withthe second word line WL1, a fine program operation (third programoperation step) may be made with respect to the first word line WL0.This is marked by {circle around (6)} in FIG. 1. Afterwards, the 1-step,coarse, and fine program operations may be performed sequentiallyaccording to the above-described program order (refer to FIG. 1). Amanner in which word lines are selected according to the program orderdescribed in FIG. 1 may be called an address scramble manner.

In an exemplary embodiment, an address scramble manner is describedunder the assumption that 3-bit data is stored in one memory cell.However, the inventive concept is not limited thereto. For example, aprogram operation performed when 4-bit data is stored in one memory cellmay be similar to that executed when 3-bit data is stored in one memorycell except that two pages of data are stored during a 2-step programoperation, and description thereof is thus omitted. In addition, thescramble order of programming the word lines need not follow the patterndescribed above. Other patterns that also do not follow the sequentialorder of the word lines can be used.

If the 1-step program operation and the 2-step program operation arecompleted, threshold voltage distributions (for example, 2^(M) thresholdvoltage distributions) corresponding to M-bit data (M being 2 or moreinteger) all may be formed. Although all threshold voltage distributionsare formed upon completion of the 2-step program operation, marginsbetween threshold voltage distributions may be insufficient todistinguish threshold voltage distributions exactly. The fine programoperation may be carried out to secure margins sufficient to distinguishthreshold voltage distributions exactly. The fine program operation maybe made to narrow a width of each threshold voltage distribution. Duringthe fine program operation, verify voltages may be used which are higherby a predetermine voltage than verify voltages of threshold voltagedistributions used at the 2-step program operation. It may be possibleto reduce the effects of coupling between adjacent memory cells throughthe above-described program manner, which is also called a reprogrammethod, or reprogram algorithm.

In an exemplary embodiment, the above-described reprogram method for3-bit data, that is, the 1-step programming, coarse programming, andfine programming may be applied to a reprogram method of other datasizes, such as, for example, 2-bit data and 4-bit data.

With the reprogram method, it may be necessary to retain data stored inmemory cells in an arbitrary word line until there is completed the fineprogram operation for the arbitrary word line. For example, the 1-stepprogram operation may be carried out depending upon data provided to amulti-bit memory device from a memory controller, and the 2-step programoperation may be made depending upon data stored through the 1-stepprogram operation and data provided from the memory controller. The fineprogram operation may be made depending upon data stored through the1-step and 2-step program operations. But, as described above, it may bedifficult to exactly read data stored through the 1-step and 2-stepprogram operations. This may mean that data necessary for the fineprogram operation should be provided to the multi-bit memory device fromthe memory controller. For this reason, the memory controller maynecessitate retaining data stored in memory cells in an arbitrary wordline until there is completed the fine program operation for thearbitrary word line. This may mean that a large buffer memory would needto be provided to the memory controller in order to retain data neededfor the fine program operation.

FIG. 2 is a diagram showing threshold voltage distributions varied whena program operation is carried out according to three-step programmingto store 3-bit data in each memory cell.

First, 2-page data (e.g., first and second page data, though other pagesmay be used) may be stored in memory cells of a selected word line(e.g., WL0 in FIG. 1). At this time, as illustrated in a box 11 of FIG.2, memory cells in a threshold voltage distribution corresponding to anerase state E may be programmed to have threshold voltages in thresholdvoltage distributions each corresponding to program states Q1, Q2, andQ3, based on data to be programmed.

As described above, a coarse program operation of 1-step programmedmemory cells in a word line (e.g., WL0) may be executed after a 1-stepprogram operation of memory cells in an adjacent word line (e.g., WL1).At this time, as illustrated in a box 12 of FIG. 2, distributions of1-step programmed memory cells in the word line (for example, WL0) maywiden due to the coupling caused when memory cells in an adjacent wordline (e.g., WL1) are programmed.

Then, 1-page data, that is, third page data may be stored in memorycells of the selected word line WL0. At this time, as illustrated in abox 13 of FIG. 2, memory cells in a threshold voltage distributioncorresponding to a previous state may be programmed to have thresholdvoltages in corresponding threshold voltage distributions. For example,memory cells in a threshold voltage distribution corresponding to anerase state E may be programmed to have threshold voltages incorresponding threshold voltage distributions to a program states P1′,based on data to be programmed. Memory cells in a threshold voltagedistribution corresponding to a program state Q1 may be programmed tohave threshold voltages in corresponding threshold voltage distributionsto program states P2′ and P3′, based on data to be programmed. Memorycells in a threshold voltage distribution corresponding to a programstate Q2 may be programmed to have threshold voltages in correspondingthreshold voltage distributions to program states P4′ and P5′, based ondata to be programmed. Memory cells in a threshold voltage distributioncorresponding to a program state Q3 may be programmed to have thresholdvoltages in corresponding threshold voltage distributions to programstates P6′ and P7′, based on data to be programmed.

As described above, a fine program operation of coarse programmed memorycells in a word line (e.g., WL0) may be performed after a 1-step programoperation and a coarse program operation on adjacent word lines (e.g.,WL1 and WL2). At this time, as illustrated by a box 14 of FIG. 2,distributions of coarse programmed memory cells in the word line (e.g.,WL0) may widen due to the coupling caused when memory cells in adjacentword lines (e.g., WL2 and WL1) are programmed. For this reason, it maybe difficult to exactly read data from coarse programmed memory cellswhen performing fine programming.

Memory cells in the word line WL0 may be programmed to have finalthreshold voltage distributions P1 to P7 as illustrated in a box 15 ofFIG. 2. This operation may be called a fine program operation. Asdescribed above, the fine program operation may need to use previouslyprogrammed data (for example, the first to third page data). Since itmay be difficult to read previously programmed data from memory cells inthe word line WL0, the fine program operation may be performed based ondata provided from a memory controller (or, data separately maintainedby a memory device).

As illustrated in a box 16 of FIG. 2, distributions of 3-step programmedmemory cells may widen due to the coupling caused when memory cells inadjacent word lines are programmed. Afterwards, a 1-step programoperation, a coarse program operation, and a fine program operation oneach word line may be made according to a program order (or, sequence)such as described, for example, in FIG. 1, which can be executed in thesame manner as described in FIG. 2.

FIG. 3 is a diagram showing threshold voltage distributions varied whena program operation is carried out according to three-step programmingto store 4-bit data in each memory cell.

First, 2-page data (i.e., first and second page data, though other pagesmay be used) may be stored in memory cells of a selected word line(e.g., WL0 in FIG. 1). At this time, as illustrated in a box 21 of FIG.3, memory cells in a threshold voltage distribution corresponding to anerase state E may be programmed to have threshold voltages in thresholdvoltage distributions each corresponding to program states Q1, Q2, andQ3, based on data to be programmed.

As described above, a coarse program operation of 1-step programmedmemory cells in a word line (for example, WL0) may be executed after a1-step program operation of memory cells in an adjacent word line (e.g.,WL1). At this time, as illustrated in a box 22 of FIG. 3, distributionsof 1-step programmed memory cells in the word line (e.g., WL0) may widendue to the coupling caused when memory cells in an adjacent word line(e.g., WL1) are programmed.

Then, 2-page data, for example, third and fourth page data, may bestored in memory cells of the selected word line WL0. At this time, asillustrated in a box 23 of FIG. 3, memory cells in a threshold voltagedistribution corresponding to a previous state may be programmed to havethreshold voltages in corresponding threshold voltage distributions. Forexample, memory cells in a threshold voltage distribution correspondingto an erase state E may be programmed to have threshold voltages incorresponding threshold voltage distributions to program states P1′ toP3′, based on data to be programmed. Memory cells in a threshold voltagedistribution corresponding to a program state Q1 may be programmed tohave threshold voltages in corresponding threshold voltage distributionsto program states P4′ to P7′, based on data to be programmed. Memorycells in a threshold voltage distribution corresponding to a programstate Q2 may be programmed to have threshold voltages in correspondingthreshold voltage distributions to program states P8′ to P11′, based ondata to be programmed. Memory cells in a threshold voltage distributioncorresponding to a program state Q3 may be programmed to have thresholdvoltages in corresponding threshold voltage distributions to programstates P12′ to P15′, based on data to be programmed.

As described above, a third step (i.e., fine) program operation ofcoarse programmed memory cells in a word line (e.g., WL0) may beexecuted after a 1-step program operation and a coarse program operationon adjacent word lines (for example, WL2 and WL1). At this time, asillustrated by a box 24 of FIG. 3, distributions of coarse programmedmemory cells in the word line (e.g., WL0) may widen due to the couplingcaused when memory cells in adjacent word lines (e.g., WL1 and WL2) areprogrammed. For this reason, it may be difficult to exactly read datafrom coarse programmed memory cells when performing fine programming.

Memory cells in the word line WL0 may be programmed to have finalthreshold voltage distributions P1 to P15 as illustrated in a box 25 ofFIG. 3. This operation may be called a fine program operation. Asdescribed above, the fine program operation may need to use previouslyprogrammed data (e.g., the first to fourth page data). Since it may bedifficult to read previously programmed data from memory cells in theword line WL0, the fine program operation may be performed based on dataprovided from a memory controller (or, data separately maintained by amemory device).

As illustrated in a box 26 of FIG. 3, distributions of fine programmedmemory cells may widen due to the coupling caused when memory cells inadjacent word lines are programmed. Afterwards, a 1-step programoperation, a coarse program operation, and a fine program operation oneach word line will be made according to a program order (or, sequence)such as described, for example, in FIG. 1, which can be executed in thesame manner as described in FIG. 3.

FIG. 4 is a block diagram showing a data storage system according to anexemplary embodiment. Referring to FIG. 4, a data storage system 100 mayinclude a host 110, a memory controller 120, and a multi-bit memorydevice 130 as a nonvolatile memory device.

The multi-bit memory device 130 may be formed of one or more memorychips. As a data storage device, the multi-bit memory device 130 and thememory controller 120 may constitute a memory card, a Solid State Drive(SSD), a memory stick, or the like. The multi-bit memory device mayinclude a plurality of memory blocks (or sectors/banks), each of whichhas memory cells arranged in rows and columns. Each of the memory cellsmay store multi-bit (or, multi-level) data. The memory cells arearranged to have the 2-dimensional array structure or the3-dimensional/vertical array structure. An exemplary 3-dimensional arraystructure is disclosed in U.S. Pat. Nos. 7,812,390 and 7,646,664, andU.S. Patent Publication Nos. 2008/0023747 and 2008/0084729, the entiretyof which are incorporated by reference herein.

Memory blocks of the multi-bit memory device 130 may be divided into aplurality of regions, such as a first region 131 and a second region133. Herein, it is well understood that division of the first and secondregions 131 and 133 is made logically, not necessarily physically.Division of the first and second regions 131 and 133 can be changedlogically. In the event that the multi-bit memory device 100 is formedof a plurality of chips or a plurality of physical regions on one ormore chips, two regions can be divided physically. The first region 131may be a hidden area which a user does not access, and the second region133 may be a user area which a user accesses.

Memory blocks in the first region 131 may be programmed in a mannerdifferent from memory blocks in the second region 133. For example,memory blocks in the first region 131 may be programmed according to asingle-bit program manner (hereinafter, referred to as an SLC programmanner), and memory blocks in the second region 133 may be programmedaccording to a multi-bit program manner (hereinafter, referred to as anMLC program manner). In addition, memory blocks in the first region 131and memory blocks in the second region 133 can be programmed accordingto the above-described N-step programming manner. Each memory cell inthe first region 131 may be designated to store and may store 1-bitdata, while each memory cell in the second region 133 may be designatedto store and may store M-bit data (M being an integer of 3 or more).Further, each memory cell in the first region 131 may store less databits in number as compared with M-bit data (M being an integer of 3 ormore) stored in each memory cell in the second region 133.

The number of blocks included in the first region 131 may be changedaccording to the number of data bits stored in memory cells of thesecond region 133. For example, if memory cells in the second region 133store N-bit data (N being an integer of 3 or more), the first region 131may include at least N memory blocks. As described further below, eachbit of the N-bit data to be stored in memory cells of the second region133 may be stored in corresponding memory blocks of the first region131, respectively. For the purposes of the discussion below, each blockof a group of blocks in the first region 131 that correspond to a singleblock in the second region 133 may be referred to as “sub-blocks.” Forexample, a first block in the second region 133 may correspond to afirst group of blocks in the first region 131 that includes threesub-blocks.

For the purposes of this discussion, it may be assumed that each memorycell of the second region 133 stores 3-bit data. In this case, the firstregion 131 may include three sub-blocks corresponding to each memoryblock of the first region 133. As an example, LSB data bits (i.e., firstdata bits) of data to be stored in memory cells of a first memory blockof the second region 133 may be stored in a first sub-block of the firstregion 131. Intermediate data bits (i.e., second data bits) of data tobe stored in memory cells of the first memory block of the second region133 may be stored in a second sub-block of the first region 131. MSBdata bits (i.e., third data bits) of data to be stored in memory cellsof the first memory block of the second region 133 may be stored in athird sub-block of the first region 131. This will be more fullydescribed later.

Continuing to refer to FIG. 4, the memory controller 120 may beconfigured to control the multi-bit memory device 130 in response to arequest of the host 110. The memory controller 120 may include a buffermemory 121. The buffer memory 121 may be used to temporarily store datasent from the host 110 and data read out from the multi-bit memorydevice 130.

The memory controller 120 may control a program operation of the memorydevice 130 in the static scheduling manner. For example, when data ofthe minimum program unit (e.g., page data) for the first region 131 isstored in the buffer memory 121, the memory controller 120 may controlthe multi-bit memory device 130 such that data of the minimum programunit is stored (or, programmed) in the first region 131. This may becalled a buffer program operation, or in some instances herein, a firstprogram operation. The buffer program operation may be performedaccording to address information associated with data stored in thebuffer memory 121. If data of the minimum program unit for the secondregion 133 is stored in the first region 131, the memory controller 120may control the multi-bit memory device 130 such that data of theminimum program unit for the second region 133 is stored (or,programmed) in the second region 133. This may be called a main programoperation, or in some instances herein, a second program operation. Themain program operation may be executed according to address informationassociated with data stored in the first region 131. The buffer programoperation and the main program operation will be more fully describedbelow.

In an exemplary embodiment, the minimum program unit for the firstregion 131 and the minimum program unit for the second region 133 may bedetermined variously depending upon a program manner, a cell-per-bitnumber, and the like. The minimum program unit for the first region 131may be different from the minimum program unit for the second region133.

In an exemplary embodiment, it may be possible to minimize a size of thebuffer memory 121 of the memory controller 120 by storing data in thefirst region 131 through the buffer program operation and storing datain the second region 133 through the main program operation. Forexample, it may be unnecessary to retain data for a three-step programoperation in the buffer memory 121. Accordingly, a size of the buffermemory 121 of the memory controller 120 may be minimized.

FIG. 5 is a diagram showing an exemplary address scramble manner of amulti-bit memory device which stores 3-bit data per cell and to which athree-step reprogram method is applied, and FIG. 6 is a diagram showingdata flow during a program operation of a data storage system where anaddress scramble manner illustrated in FIG. 5 is applied. Below, aprogram operation of a data storage system according to anotherexemplary embodiment will be more fully described with reference toaccompanying drawings.

For ease of description, as illustrated in FIG. 5, it is assumed thateach of the memory blocks included in a first region 131 and a secondregion 133 includes 64 word lines WL0 to WL63, that each memory cell inthe first region 131 stores 1-bit data, and that each memory cell in thesecond region 133 stores 3-bit data. With this assumption, 192 pages arestored in each memory block in the second region 133, and those 192pages may also be stored across three sub-blocks of the first region131. As described above, since each memory cell of the second region 133stores 3-bit data, in one embodiment, the first region 131 may includethree memory blocks (e.g., sub-blocks) corresponding to each memoryblock of the second region 133. A first block BLK0 of the first region131 may be used to store LSB page data of 3-bit data to be stored at afirst block of the second region 133, a second block BLK1 of the firstregion 131 may be used to store intermediate page data of the 3-bit datato be stored at the first block of the second region 133, and a thirdblock BLK2 of the first region 131 may be used to store MSB page data ofthe 3-bit data to be stored at a first block of the second region 133.Based on an exemplary structure where each block includes K word lines,N×K word lines may be used in the first region 131 to represent the samenumber of pages (e.g., N pages) of data as K word lines in the secondregion 133. In one embodiment, each of the K word lines in the secondregion 133 may store N bits of data.

As described in FIGS. 4 and 5, directly after page data Di (i being 0 to191) for the first region 131 is stored in a buffer memory 121 of amemory controller 120, data Di stored in the buffer memory 121 may beprogrammed in the first region 131 of a multi-bit memory device 130through an SLC program operation. As described above, the page data Dimay be stored in the first region 131 via the SLC program operation.

In one embodiment, at a buffer program operation, a memory block (e.g.,sub-block) of the first region 131, in which page data Di is to bestored, may be determined according to an order of page data Di as itrelates to multi-level data. For example, page data Di corresponding toan LSB bit of the multi-level data may be stored in a block BLK0 of thefirst region 131. Page data Di corresponding to an intermediate bit ofthe multi-level data may be stored in a block BLK1 of the first region131. Page data Di corresponding to an MSB bit of the multi-level datamay be stored in a block BLK2 of the first region 131. Further, at thebuffer program operation, a word line in which page data Di is to bestored may be determined according to a word line of the second region133 in which page data Di is stored via a main program operation. Forexample, at the buffer program operation, page data Di may be stored ina word line of the first region 131 which is identical in relativelocation to a word line of the second region 133 (e.g., both regions mayinclude same-sized blocks, and the page data Di may be stored in thesame word line for each block). For example, the two word lines may bothhave the same row address, or word line address. This buffer programoperation according to an exemplary embodiment may be referred to as aparallel buffer program operation.

The memory controller 200 may judge whether page data for the secondregion 133 is gathered at the first region 131. A main program operationfor the second region 133, for example, a 1-step program operation, acoarse program operation, or a fine program operation may be carried outaccording to the judgment result. In certain embodiments, 1-step programoperation, a coarse program operation, or a fine program operation forthe second region 102 may be determined according to an address scrambleorder such as illustrated in FIG. 5.

Referring to FIGS. 5 and 6, if page data D0 for the first region 131 istransferred to a buffer memory 121 of a memory controller 120 from ahost 110, it may be programmed in the first region 131 according to thecontrol of the memory controller 120. The page data D0 may be page datato be stored in a word line WL0 (refer to FIG. 5), and may be formed ofan LSB bit of multi-level data. For this reason, the page data D0 may beprogrammed at the word line WL0 of a first block BLK0 of the firstregion 131.

The memory controller 120 may judge whether page data for the secondregion 133 is gathered at the first region 131 and control a mainprogram operation according to the judgment result. Since one page ofdata D0 is stored in the first region 131, no main program operation maybe carried out.

When page data D1 for the first region 131 is transferred to the buffermemory 121 of the memory controller 120 from the host 110, it may beprogrammed in the first region 131 according to the control of thememory controller 120. The page data D1 may be page data to be stored ina word line WL0 (refer to FIG. 5), and may be formed of an intermediatebit of multi-level data. For this reason, the page data D1 may beprogrammed at a word line WL0 of a second block BLK1 of the first region131.

Since page data (e.g., two pages of data for a 1-step program operation)for the second region 133 is gathered at the first region 131, thememory controller 120 may control the multi-level memory device 130 suchthat page data D0 and D1 stored in the first region 131 are programmedin the second region 133. As such, a 1-step program operation for theword line WL0 may be carried out depending upon two pages of data D0 andD1 stored in the first region 131.

Next, page data D2 may be programmed at a word line WL1 of the firstblock BLK0 of the first region 131, and page data D3 may be programmedat a word line WL1 of the second block BLK1 of the first region 131.Since page data (e.g., two pages of data for a 1-step program operation)for the second region 133 is gathered at the first region 131, thememory controller 120 may control the multi-level memory device 130 suchthat page data D2 and D3 stored in the first region 131 are programmedin the second region 133. That is, a 1-step program operation for theword line WL1 may be carried out depending upon two pages of data D2 andD3 stored in the first region 131.

When page data D4 for the first region 131 is transferred to the buffermemory 121 of the memory controller 120 from the host 110, it may beprogrammed in the first region 131 according to the control of thememory controller 120. The page data D4 may be data to be stored in aword line WL0 (refer to FIG. 5), and may be formed of an MSB bit of themulti-level. For this reason, the page data D4 may be programmed at aword line WL0 of a third block BLK2 of the first region 131.

Since page data (e.g., three pages of data for a coarse programoperation) for the second region 133 is gathered at the first region131, the memory controller 120 may control the multi-level memory device130 such that page data D0, D1, and D4 stored in the first region 131are programmed in the second region 133. A coarse program operation forthe word line WL0 may be carried out depending upon three pages of dataD0, D1, and D4 stored in the first region 131.

Next, page data D5 may be programmed at a word line WL2 of the firstblock BLK0 of the first region 131, and page data D6 may be programmedat a word line WL2 of the second block BLK1 of the first region 131.Since page data (e.g., two pages of data for a 1-step program operation)for the second region 133 is gathered at the first region 131, thememory controller 120 may control the multi-level memory device 130 suchthat page data D5 and D6 stored in the first region 131 are programmedin the second region 133. As such, a 1-step program operation for theword line WL2 may be carried out depending upon two pages of data D5 andD6 stored in the first region 131.

Page data D7 may be programmed at a word line WL1 of a third block BLK2of the first region 131. Since page data (e.g., three pages of data fora coarse program operation) for the second region 133 is gathered at thefirst region 131, the memory controller 120 may control the multi-levelmemory device 130 such that page data D2, D3, and D7 stored in the firstregion 131 are programmed in the second region 133. As such, a coarseprogram operation for the word line WL1 may be carried out dependingupon three pages of data D2, D3, and D7 stored in the first region 131.

After a coarse program operation for the word line WL1 is carried out, afine program operation may be executed depending upon data D0, D1, andD4 stored in the first region 131. Afterwards, the 1-step, coarse, andfine program operations for remaining page data D8 to D190 may beperformed in the same manner as described above, until page data D191 isstored at the first region 131.

Page data D191 may be programmed at a word line WL63 of the third blockBLK2 of the first region 131. Since page data (e.g., three pages of datafor a 2-step program operation) for the second region 133 is gathered atthe first region 131, the memory controller 120 may control themulti-level memory device 130 such that page data D188, D189, and D191stored in the first region 131 are programmed in the second region 133.That is, a 2-step program operation for the word line WL63 may becarried out depending upon three pages of data D188, D189, and D191stored in the first region 131.

After a coarse program operation for the word line WL63 is carried out,a fine program operation for a word line WL62 may be executed dependingupon data D185, D186, and D190 stored in the first region 131. Finally,a fine program operation for the word line WL63 may be executeddepending upon data D188, D189, and D191 stored in the first region 131.

As a result of this process, in one embodiment, a memory block of an MLCregion of a memory device can be programmed using a plurality of memoryblocks in a SLC region of the memory device, wherein the number ofmemory blocks in the SCL region used for programming the block in theMLC region is equal to the number of bits per cell of the memory cellsin the MLC region. This can provide direct mapping between word lines ofthe blocks in the SLC region and word lines of the block in the MLCregion, which can improve programming speed.

FIG. 7 is a flow chart for describing a read operation of a memorysystem illustrated in FIG. 4, according to one exemplary embodiment.

In step S100, a read operation may be requested from an external device(e.g., a host). In step S110, a memory controller 120 may judge whetherthe read request is related to a word line whose three-step programoperation is completed. Whether the three-step program operation foreach word line is completed may be judged depending upon address mappinginformation.

In the event that the read request is associated with a word line whosethree-step program operation is completed, in step S120, the memorycontroller 120 may control a multi-bit memory device 130 such thatrequested data is read from a second region 133 of the memory device100. The read operation for the second region 133 may be an MLC readoperation. Data read from the second region 133 may be temporarilystored in a buffer memory 121 of the memory controller 120. Afterwards,the procedure goes to step S140.

Returning to step S110, if the read request is associated with a wordline whose three-step program operation is not completed (e.g., fineprogramming has not been completed), in step S130, the memory controller120 controls the multi-bit memory device 130 such that requested data isread from the first region 131. The read operation for the first region131 may be an SLC read operation. Data read from the first region 131may be temporarily stored in the buffer memory 121 of the memorycontroller 120. Afterwards, the procedure goes to step S140, in whichdata stored in the buffer memory 121 is sent to the external device,that is, the host 110. As a result, pages of data that have been writtento the memory device 100 but that have not yet been stored in the MLCregion can still be properly read from the device.

FIGS. 8 and 9 are diagrams illustrating exemplary data flow according toa set of a parallel buffer program operations and a main programoperation described in FIG. 6. FIGS. 10 and 11 are diagrams illustratinga bias condition at a parallel buffer program operation according to anexemplary embodiment.

Referring to FIG. 8, page data D0 may be loaded onto a page buffer 135of a multi-level memory device 130. The loaded page data D0 of the pagebuffer 135 may be stored in a word line WL0 of a first block 131_0 of afirst region 131. Page data D1 may be loaded onto the page buffer 135 ofthe multi-level memory device 130. The loaded page data D1 of the pagebuffer 135 may be stored in a word line WL0 of a second block 131_1 ofthe first region 131.

As described in relation to FIGS. 5 and 6, a word line, in which pagedata D0 and D1 are to be stored, may be the same as that of a secondregion 133 in which data D0 and D1 is to be stored via a main programoperation (e.g., it may have an identical relative location (physicallyand/or logically) and/or row address within a same-sized block). Forthis reason, the page data D0 and D1 may be stored in word lines WL0 ofdifferent blocks 131_0 and 131_1 of the first region 131. With thisparallel buffer program operation, as illustrated in FIG. 11, the pagedata D0 and D1 may be stored at the same word line WL0 by changing ablock address from BLK0 to BLK1. In other words, it is possible toprogram two pages of data D0 and D1 by generating a program voltage Vpgmand a pass voltage Vpass once. For example, as shown in FIG. 6, betweenthe steps of programming D0 to WL0 of a first block of the first region131 and programming D1 to WL0 of a second block of the first region 131,word lines can maintain a program voltage Vpgm and a pass voltage Vpassat a constant level, instead of needing to be changed to a differentvoltage and then reset to Vpgm and Vpass. For this reason, there may bereduced a setup time and a reset time (e.g., a recovery time) needed togenerate the program voltage Vpgm and the pass voltage Vpass,respectively.

Continuing to refer to FIG. 8, if two pages of data D0 and D1 are storedin the first region 131, for example, if page data for the second region133 (e.g., two pages of data for a 1-step program operation) is gatheredat the first region 131, the two pages of data D0 and D1 may besequentially read by the page buffer 135. This read operation may bereferred to as a parallel buffer read operation. With the parallelbuffer read operation, as illustrated in FIG. 10, the page data D0 andD1 may be read by changing a block address from BLK0 to BLK1. In otherwords, it is possible to read two pages of data D0 and D1 by generatinga selection read voltage Vrd and a non-selection read voltage Vreadonce. For this reason, there may be reduced a setup time and a resettime (e.g., a recovery time) needed to generate the selection readvoltage Vrd and the non-selection read voltage Vread, respectively.

Returning to FIG. 8, two pages of data D0 and D1 stored in the pagebuffer 135 may be stored in the second region 133 according to a 1-stepprogram operation of the main program operation.

Referring to FIG. 9, page data D4 may be loaded onto the page buffer 135of the multi-level memory device 130. The loaded page data D4 of thepage buffer 135 may be stored at a word line WL0 of a third block 131_2of the first region 131. As described in relation to FIGS. 5 and 6, aword line, in which page data D4 is to be stored, may be identical tothat of the second region 133 in which data D4 is to be stored via themain program operation. For this reason, the page data D4 may be storedin a word line of a block (i.e., a third block 131_2) different from ablock in which the page data D0 and D1 is stored.

If page data for the second region 133 (e.g., three pages of data for athree-step program operation) is gathered at the first region 131, thethree pages of data D0, D1, and D4 may be sequentially read by the pagebuffer 135. With the parallel buffer read operation, as illustrated inFIG. 10, the page data D0, D1, and D4 may be read by changing a blockaddress from BLK0 to BLK2. As a result, it is possible to read threepages of data D0, D1, and D4 by generating the selection read voltageVrd and the non-selection read voltage Vread once. In the methoddescribed above, a plurality of pages (e.g., three pages) aredivisionally stored in a plurality of corresponding memory blocks (e.g.,at least one page is stored in each memory block). Because the firstpage data D0, the second page data D1, and later the third page data D4are stored in the same word line (WL0) with respect to their respectiveblocks, the process of storing the data D0, D1, and D4 may be referredto herein as a co-locational storage process. Similarly the process ofreading the data D0, D1, and D4 from the same relative word line in eachblock may be referred to herein as a co-locational read process.

Continuing to refer to FIG. 9, three pages of data D0, D1, and D4temporarily stored in the page buffer 135 may be stored in the secondregion 133 according to a second-step (i.e., coarse) program operationof the main program operation. A third-step (i.e., fine) programoperation may be carried out in the same manner as the second-stepprogram operation. For example, a fine program operation for a word lineWL0 of the second region 133 may be performed by sequentially readingthree pages of data D0, D1, and D4 via the parallel buffer readoperation and programming the three pages of data D0, D1, and D4 storedin the page buffer 135 in the second region 133.

FIGS. 8 and 9 therefore illustrate a method of storing data in a datastorage system. The method includes providing a memory cell array. Themethod further includes providing N blocks in a first region of thememory cell array (e.g., BLK0, BLK1, and BLK2). N may be an integergreater than 1, and each cell of each block of the N blocks may beconfigured to store no more than N−1 bits of data (e.g., they may be SLCcells that store only 1 bit of data). The method additionally includesproviding a block in the second region of the memory cell array. Eachcell of the block in the second region may be configured to store N bitsof data (e.g., they may be MLC cells that store 3 bits of data). Thedata storage system is configured (for example, at a manufacturing stageor later) so that when data is programmed to the memory cell array, Npages of the data are initially stored in N respective blocks of thefirst region of the memory cell array, and then the N pages of the dataare stored in the block of the second region.

In one embodiment, each block of the N blocks includes K word lines, andthe block in the second region includes K word lines. The data storagemay be configured so that when data is programmed to the memory cellarray, the N pages of the data are initially stored in Mth word lines(e.g., WL0) of each of the N respective blocks of the first region ofthe memory cell array, and then the N pages of the data are stored in anMth word line (e.g., WL0) of the block of the second region. Storing theN pages of the data in the block of the second region may includereading the N pages of the data from the N blocks of the first region,and then programming the data read from the N blocks of the first regionto the block of the second region.

FIG. 12 is a diagram for describing a command provided to a multi-levelmemory device to perform a program operation that includes a parallelbuffer program/read operation according to an exemplary embodiment.

Referring to FIG. 12, there are illustrated commands for controlling aparallel buffer program operation, a parallel buffer read operation, anda main program operation. The commands may be provided to a multi-levelmemory device 130 (refer to FIG. 4) from a memory controller 120 (referto FIG. 4).

A parallel buffer program/read start command PBSh for a parallel bufferprogram/read operation may be provided to the multi-level memory device130. Once the parallel buffer program/read start command PBSh isprovided, the multi-level memory device 130 may perform a parallelbuffer program operation although typical program commands 80 h and 10 hare received. Further, if the parallel buffer program/read start commandPBSh is provided, the multi-level memory device 130 may perform aparallel buffer read operation although typical read commands 00 h and30 h are received. As such, in the embodiment shown in FIG. 12, a singlestart command may be received that instructs the memory to treatsubsequent commands as related to a parallel program and read sequence(until an end command is received). The start and end commands may eachbe referred to as a mode-switching command. As discussed previously, asingle address can be received in the parallel program and readsequences. The single address can be used to store data to and accessdata from co-located word lines within different memory blocks. Becausethe parallel buffer program/read start command (i.e., mode-switchingcommand) has been received, the data received can be appropriatelyprogrammed to and read from a plurality of memory blocks using thereceived address.

After the parallel buffer read operation is carried out, the programcommands 80 h and 10 h may be provided to the multi-level memory device130. A main program operation may be discriminated from a parallelbuffer program operation according to data (or, a page addressassociated with the data) to be stored in a second region 133. If themain program operation is completed, a parallel buffer program/readcommand PBEh may be provided to the multi-level memory device 130 to endthe parallel buffer program/read operation.

In one embodiment, the parallel buffer read operation and the mainprogram operations (e.g., the 1-step program operation, the coarseprogram operation, and/or the fine program operation) may be performedautomatically within the multi-level memory device 130 withoutintervention of the memory controller 120. In another embodiment, theparallel buffer read operation and the main program operation (e.g., the1-step program operation, the coarse program operation, and/or the fineprogram operation) may be performed according to the control of thememory controller 120.

FIG. 13 is a diagram for describing another command provided to amulti-level memory device to perform a program operation that includes aparallel buffer program/read operation according to an exemplaryembodiment.

Referring to FIG. 13, there are illustrated commands for controlling aparallel buffer program operation and a parallel buffer read operation.The command may be provided to a multi-level memory device 130 (refer toFIG. 4) from a memory controller 120 (refer to FIG. 4).

Parallel buffer program commands PBP1 h and PBP2 h for controlling theparallel buffer program operation may be provided to the multi-levelmemory device 130. In another embodiment, the parallel buffer programcommand PBP1 h and a typical program command (e.g., 10 h) may besequentially provided to the multi-level memory device 130. In stillanother embodiment, a typical program command (e.g., 80 h) and theparallel buffer program command PBP2 h may be sequentially provided tothe multi-level memory device 130. If the commands are provided, themulti-level memory device 130 may perform a parallel buffer programoperation as described above.

Prior to a main program operation, parallel buffer read commands PBR1 hand PBR2 h for controlling a parallel buffer read operations may beprovided to the multi-level memory device 130. In another embodiment,the parallel buffer read command PBR1 h and a typical read command(e.g., 30 h) may be sequentially provided to the multi-level memorydevice 130. In still another embodiment, a typical read command (e.g.,00 h) and the parallel buffer read command PBR2 h may be sequentiallyprovided to the multi-level memory device 130. If the commands areprovided, the multi-level memory device 130 may perform a parallelbuffer read operation as described above.

In other words, the parallel buffer program operation and the parallelbuffer read operation may be performed when corresponding commands areprovided to the multi-level memory device 130 from the memory controller120. The main program operation may be carried out when a typicalprogram command is provided to the multi-level memory device from thememory controller 120. The embodiment of FIG. 13 differs from theembodiment of FIG. 12 in that it includes individual parallel programand parallel read commands at different stages in the overall programoperation, instead of using only one overall parallel program/readcommand that applies to the overall program operation.

FIGS. 14 to 17 are diagrams for describing various combinations on firstand second regions of a multi-bit memory device according to exemplaryembodiments. In figures, “BP” indicates buffer programming on a firstregion 131, and “MP” indicates main programming on a second region 133.

In one embodiment, a multi-bit memory device 130 is a semiconductor chiphaving one or more memory cell arrays. As described above, the multi-bitmemory device 130 may include the first region 131 and the second region133. The first and second regions 131 and 133 may constitute a memorycell array of the multi-bit memory device 130. Although not illustratedin the figures, the memory cell array may include further regions suchas a meta region, a reserved region, and the like. It is well understoodthat regions of the memory cell array are divided logically, notnecessarily physically. This means that such regions of the memory cellarray may be defined according to address mapping of a memory controller120.

Referring to FIG. 14, in case of a multi-bit memory device 130 whichstores 3-bit data per cell, the first region 131 is formed of memorycells each storing 1-bit data, and the second region 133 is formed ofmemory cells each storing 3-bit data. In this case, buffer programmingmay be executed according to an SLC program manner, and main programmingmay be made according to the above-described MLC program manner.

Referring to FIG. 15, in case of a multi-bit memory device 130 whichstores 4-bit data per cell, the first region 131 is formed of memorycells each storing 1-bit data, and the second region 133 is formed ofmemory cells each storing 4-bit data. In this case, buffer programmingmay be executed according to an SLC program manner, and main programmingmay be made according to the above-described MLC program manner.

Referring to FIG. 16, in case of a multi-bit memory device 130 whichstores 3-bit data per cell, the first region 131 is formed of memorycells each storing 2-bit data, and the second region 133 is formed ofmemory cells each storing 3-bit data. In this case, buffer programmingmay be executed according to the above-described or conventional MLCprogram manner, and main programming may be made according to theabove-described MLC program manner (for example, a reprogram manner).

Referring to FIG. 17, in case of a multi-bit memory device 130 whichstores 4-bit data per cell, the first region 131 is formed of memorycells each storing 2-bit data, and the second region 133 is formed ofmemory cells each storing 4-bit data. In this case, buffer programmingmay be executed according to the above-described or conventional MLCprogram manner, and main programming may be made according to theabove-described MLC program manner (for example, a reprogram manner).

In an exemplary embodiment, it is well understood that defining of thefirst and second regions 131 and 133 illustrated in FIGS. 14 to 17 isnot limited to this disclosure. For example, if a nonvolatile memorydevice included in a data storage system 100 (refer to FIG. 4) is formedof a plurality of multi-bit memory devices, the first and second regions131 and 133 can be defined with respect to the respective multi-bitmemory devices (e.g., different memory chips or packages).Alternatively, the first region 131 can be defined with respect to anyone of the multi-bit memory devices. Still alternatively, any onemulti-bit memory device can be defined as the first region 131.

FIG. 18 is a diagram illustrating a memory cell array having the all bitline memory architecture or the odd-even memory architecture. Exemplarystructures of a memory cell array included in a multi-bit memory device130 illustrated in FIG. 4 will be described. As one example, a NANDflash memory device including a memory cell array 110 partitioned into1,024 blocks will now be described. The data stored in each block may besimultaneously erased. In one embodiment, the memory block is theminimum unit of storage elements that are simultaneously erased. Eachmemory block, for example, has columns each corresponding to bit lines(e.g., bit lines of 1KB). In one embodiment referred to as the all bitline (ABL) architecture, all the bit lines of a memory block are capableof being simultaneously selected during read and program operations.Storage elements in a common word line and connected to all bit linesare capable of being programmed at the same time.

In an exemplary embodiment, a plurality of storage elements in the samecolumn are connected in series to form a NAND string 111. One end of theNAND string 111 is connected to a corresponding bit line via a selecttransistor which is controlled by a string select line SSL, the otherend is connected to a common source line CSL via a select transistorwhich is controlled by a ground select line GSL.

In another embodiment referred to as the odd-even architecture, bitlines are divided into even bit lines (BLe) and odd bit lines (BLo). Inthe odd/even bit line architecture, storage elements in a common wordline and connected to the odd bit lines are programmed at the firsttime, while storage elements in the common word line and connected toeven bit lines are programmed at the second time. Data is capable ofbeing programmed to and read from different blocks. Such operations arecapable of being performed at the same time.

A flash memory device forming a multi-bit memory device 130 may be anonvolatile memory device which retains data even at power-off. With anincrease in mobile devices such as cellular phone, PDA digital camera,portable gate console, and MP3P, a flash memory device is widely used asnot only data storage but also code storage. The flash memory device,further, is capable of being used at home applications such as HDTV,DVD, router, and GSP.

FIG. 19 is a block diagram showing a computing system according to anexemplary embodiment.

A computing system may include a processing unit 2100 (e.g., amicroprocessor), a user interface 2200, a modem 2300 such as a basebandchipset, a memory controller 2400, and a multi-bit memory device 2500 asa storage media. In one embodiment, the multi-bit memory device 2500 maybe configured the same as illustrated in FIG. 4. For example, a size ofa buffer memory included in the memory controller 2400 can be minimized.N-bit data (N being 1 or more integer) processed/to be processed by themicroprocessor 2100 may be stored in the multi-bit memory device 2500through the memory controller 2400. In the event that the computingsystem is a mobile device, a battery 2600 may be further included in thecomputing system to supply an operating voltage thereto. Although notillustrated in FIG. 19, the computing system may further comprise anapplication chipset, a camera image processor (CIS), a mobile DRAM, andthe like.

FIG. 20 is a block diagram showing a memory controller according to anexemplary embodiment. Referring to FIG. 20, a controller may beconfigured to store data in a storage media and read data from thestorage media. The controller may include a first interface 3210, asecond interface 3220, a processing unit 3230, a buffer memory 3240, anECC unit 3250, and a ROM 3260. The memory controller in FIG. 20 may beapplied to a system such as that illustrated in FIG. 4 or 19.

The first interface 3120 may be configured to interface with an externaldevice (for example, a host), and the second interface 3220 may beconfigured to interface with the storage media 3100, for example astorage media such as illustrated in FIG. 4 or 19. The processing unit3230 may be configured to control an overall operation of the controller3200. The processing unit 3230 may be configured to operate firmwaresuch as Flash Translation Layer (FTL) stored in the ROM 3260. The buffermemory 3240 may be used to temporarily store data to be written in thestorage media 3100 or data read out from the storage media 3100. The ECCunit 3250 may be configured to encode data to be stored in the storagemedia 3100 and to decode data read from the storage media 3100.

In one embodiment, the memory controller may be configured tosequentially generate commands according to a command sequence such asdescribed in FIGS. 12 and 13.

FIG. 21 is a block diagram showing a solid state drive according toexemplary embodiments. Referring to FIG. 21, a solid state drive (SSD)4000 may comprise a storage media 4100 and a controller 4200.

The storage media 4100 may be connected with the controller 4200 via aplurality of channels, each of which is commonly connected with aplurality of nonvolatile memories. Each nonvolatile memory device may beformed of a memory such as described in FIG. 4. The controller 4200 maybe configured to control the storage media 4100 according to any one ofprogramming manners described above with reference to FIGS. 5 to 13. Asa result, a size of a buffer memory included in the controller 4200 canbe minimized.

FIG. 22 is a block diagram showing a storage using a solid state drivein FIG. 21, and FIG. 23 is a block diagram showing a storage serverusing a solid state drive in FIG. 21, according to certain embodiments.

An SSD 4000 according to an exemplary embodiment may be used to form thestorage. As illustrated in FIG. 22, the storage may include a pluralityof solid state drives 4000 which are configured the same as described inFIG. 21. An SSD 4000 according to an exemplary embodiment may be used toconfigure a storage sever. As illustrated in FIG. 23, an exemplarystorage server includes a plurality of solid state drives 4000, whichmay be configured the same as described in FIG. 21, and a server 4000A.Further, it is well comprehended that a well-known RAID controller 4000Bmay be provided in the storage server.

FIGS. 24 to 26 are diagrams showing systems to which a data storagedevice according to exemplary embodiments may be applied.

In the event that a solid state drive including a data storage deviceformed of a memory controller and a multi-bit memory device according toexemplary embodiments is applied to the storage, as illustrated in FIG.24, a system 6000 may include a storage 6100 which communicates with ahost by a wire or wireless manner. In a case where a solid state driveincluding a data storage device according to exemplary embodiments isapplied to a storage server, as illustrated in FIG. 25, a system 7000may include a storage servers 7100 and 7200 which communicate with ahost by a wire or wireless manner (e.g., over a network such as anintranet or the Internet). Further, as illustrated in FIG. 26, a solidstate drive including a data storage device according to exemplaryembodiments can be applied to a mail server 8100.

FIG. 27 is a block diagram illustrating a memory card according toexemplary embodiments.

A memory card, for example, may be an MMC card, an SD card, a multiusecard, a micro-SD card, a memory stick, a compact SD card, an ID card, aPCMCIA card, an SSD card, a chip-card, a smartcard, an USB card, or thelike.

Referring to FIG. 27, the memory card may include an interface circuit9221 for interfacing with an external device, a controller 9222including a buffer memory and controlling an operation of the memorycard, and at least one nonvolatile memory device 9207 according toembodiments discussed above. The controller 9222 may be coupled with thenonvolatile memory device 9207 and the interface circuit 2221 via a databus and an address bus.

As a processor, the controller 9222 may control program and readoperations of the nonvolatile memory device 9208. The controller 9222and the non-volatile memory device 9207 may correspond to a controller120 and a multi-bit memory device 130 described in FIG. 4, respectively.The controller 9222 may be configured to control the non-volatile memorydevice 9207 according to any one of programming manners described abovewith reference to FIGS. 5 to 13. This means that a size of a buffermemory included in the controller 9222 can be minimized.

FIG. 28 is a block diagram illustrating a digital still camera accordingto certain embodiments.

Referring to FIG. 28, a digital still camera may include a body 9301, aslot 9302, a lens 9303, a display circuit 9308, a shutter button 9312, astrobe 9318, and the like. In particular, a memory card 9331 may beinserted in the slot 9308 and include a memory controller 120 and amulti-bit memory device 130 described in FIG. 4.

The memory controller in the memory card 9331 may be configured tocontrol the multi-bit memory device therein according to any one ofprogramming manners described with reference to FIGS. 5 to 13. Thismeans that a size of a buffer memory included in the memory controllercan be minimized.

If the memory card 9331 has a contact type, an electric circuit on acircuit board may be electrically contacted with the memory card 9331when it is inserted in the slot 9308. In the event that the memory card9331 has a non-contact type, an electric circuit on a circuit board maycommunicate with the memory card 9331 in a radio-frequency manner.Although a digital still camera is depicted, the same principles andelements could be used in a camera that records moving pictures (i.e.,video).

FIG. 29 is a diagram illustrating various systems to which a memory cardin FIG. 28 may be applied.

Referring to FIG. 29, a memory card 9331 may be applied to a videocamera, a television, an audio device, a game machine, an electronicmusic device, a cellular phone, a computer, a Personal Digital Assistant(PDA), a voice recorder, a PC card, and the like.

A nonvolatile memory device and/or a memory controller according to thedisclosed embodiments may be packed using various types of packages. Forexample, A non-volatile memory device or a memory controller accordingto certain embodiments may be packed using packages such as PoP (Packageon Package), Ball grid arrays (BGAs), Chip scale packages (CSPs),Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP),Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic DualIn-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), SmallOutline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi ChipPackage (MCP), Wafer-level Fabricated Package (WFP), Wafer-LevelProcessed Stack Package (WSP), and the like.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope. Thus, the scope is to be determined by thebroadest permissible interpretation of the following claims and theirequivalents, and shall not be restricted or limited by the foregoingdetailed description.

1. A data storage system comprising: a nonvolatile memory deviceincluding a memory cell array; and a memory controller configured tocontrol the nonvolatile memory device, wherein the memory cell arrayincludes a first region configured for storing up to N−1-bit data (Nbeing an integer greater than 1) per memory cell and a second regionconfigured for storing N-bit data per memory cell, the first regionincluding N memory blocks; wherein the memory controller is configuredto control the nonvolatile memory device to perform a buffer programoperation in which N-bit data to be stored in the second region isdivisionally stored in the N memory blocks of the first region, and amain program operation in which the N-bit data stored in the firstregion is stored in the second region; and wherein the memory controlleris configured to control the nonvolatile memory device to divisionallystore, during the buffer program operation, the N-bit data at a wordline of each of the N memory blocks of the first region disposed at thesame relative location, with respect to each block, as a word line ofthe second region in which the N-bit data is to be stored.
 2. The datastorage system of claim 1, wherein the memory controller comprises abuffer memory; and wherein the memory controller is configured to: causethe buffer program operation to occur after data of a minimum programunit of the first region is stored in the buffer memory, and during thebuffer program operation, control the nonvolatile memory device suchthat data stored in the buffer memory is stored in the first region. 3.The data storage system of claim 2, wherein the memory controller isconfigured to: cause the main program operation to occur after data of aminimum program unit of the second region is stored in the first region,and during the main program operation, control the nonvolatile memorydevice such that data stored in the first region is stored in the secondregion.
 4. The data storage system of claim 1, wherein the main programoperation includes at least one of a 1-step program operation, a coarseprogram operation, and a fine program operation.
 5. The data storagesystem of claim 1, wherein the first region is configured to beprogrammed according to a single-bit program manner and the secondregion is configured to be programmed according to a multi-bit programmanner.
 6. The data storage system of claim 1, wherein the first regionincludes only N memory blocks, and N is identical to the number of bitsthat the nonvolatile memory device is configured to store in each memorycell of the second region.
 7. The data storage system of claim 1,wherein: each block of the N memory blocks of the first region includesK word lines, and the second region includes K word lines.
 8. Anoperating method of a data storage system that includes a nonvolatilememory device having a memory cell array divided into a first region anda second region, and a memory controller configured to control thenonvolatile memory device, the operating method comprising: performing afirst program operation in which N-bit data (N being a positive integergreater than 1) to be stored in the second region is divisionally storedin each of at least N memory blocks included in the first region; andperforming a second program operation in which the N-bit data stored inthe first region is stored in the second region, wherein performing thefirst program operation includes divisionally storing the N-bit data ata word line of each of the N memory blocks of the first region disposedat the same location relative to the memory block in which it isincluded as a word line of the second region in which the N-bit data isto be stored.
 9. The operating method of claim 8, wherein performing thesecond program operation comprises: sequentially reading the N-bit datastored in the first region from the N memory blocks; and storing theread N-bit data in the second region.
 10. The operating method of claim8, wherein the second program operation is performed by at least one ofa 1-step program operation, a coarse program operation, and a fineprogram operation.
 11. The operating method of claim 8, furthercomprising: outputting a mode switching command for use in the firstprogram operation to the nonvolatile memory device before a set ofprogram commands for the first program operation are output to thenonvolatile memory device.
 12. The operating method of claim 11, whereinwhen the second program operation is carried out, the set of commandsoutput to the nonvolatile memory device comprises a read command for thefirst region and a program command for the second region.
 13. Theoperating method of claim 12, further comprising: outputting a modeswitching command for ending of the first program operation to thenonvolatile memory device after the second program operation is carriedout.
 14. The operating method of claim 8, wherein each of memory cellsof the first region stores M-bit data and each of memory cells of thesecond region stores N-bit data, M being less than N.
 15. The operatingmethod of claim 14, wherein the first region is programmed according toa single-bit program manner and the second region is programmedaccording to a multi-bit program manner.
 16. A method for a data storagesystem, the method including: providing a memory cell array; providing Nblocks in a first region of the memory cell array, N being an integergreater than 1, wherein: each cell of each block of the N blocks isconfigured to store no more than N−1 bits of data; providing a block inthe second region of the memory cell array, wherein: each cell of theblock in the second region is configured to store N bits of data; andconfiguring the data storage system so that when data is programmed tothe memory cell array, N pages of the data are initially stored in Nrespective blocks of the first region of the memory cell array, and thenthe N pages of the data are stored in the block of the second region.17. The method of claim 16, wherein: each block of the N blocks includesK word lines, and the block in the second region includes K word lines.18. The method of claim 17, further comprising: configuring the datastorage system so that when data is programmed to the memory cell array,the N pages of the data are initially stored in Mth word lines of eachof the N respective blocks of the first region of the memory cell array,and then the N pages of the data are stored in an Mth word line of theblock of the second region.
 19. The method of claim 16, wherein storingthe N pages of the data in the block of the second region includesreading the N pages of the data from the N blocks of the first region,and then programming the data read from the N blocks of the first regionto the block of the second region.
 20. The method of claim 16, whereinthe memory cell array comprises one or more layers of memory cells thatare part of a semiconductor chip or a package including stackedsemiconductor chips.